An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 10. Each cell 10 contains a storage capacitor 14 and an access field effect transistor or transfer device 12. For each cell, one side of the storage capacitor 14 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor 14 is connected to the drain of the transfer device 12. The gate of the transfer device 12 is connected to a signal known in the art as a word line 18. The source of the transfer device 12 is connected to a signal known in the art as a bit line 16 (also known in the art as a digit line). With the memory cell 10 components connected in this manner, it is apparent that the word line 18 controls access to the storage capacitor 14 by allowing or preventing the signal (representing a logic “0” or a logic “1”) carried on the storage capacitor 14 to be read to or written from the bit line 16. Thus, each cell 10 contains one bit of data (i.e., a logic “0” or logic “1”).
Referring to FIG. 2, an exemplary DRAM circuit 40 is illustrated. The DRAM 40 contains a memory array 42, row and column decoders 44, 48 and a sense amplifier circuit 46. The memory array 42 consists of a plurality of memory cells (constructed as illustrated in FIG. 1) whose word lines and bit lines are commonly arranged into rows and columns, respectively. The bit lines of the memory array 42 are connected to the sense amplifier circuit 46, while its word lines are connected to the row decoder 44. Address and control signals are input into the DRAM 40 and connected to the column decoder 48, sense amplifier circuit 46 and row decoder 44 and are used to gain read and write access, among other things, to the memory array 42.
The column decoder 48 is connected to the sense amplifier circuit 46 via control and column select signals. The sense amplifier circuit 46 receives input data destined for the memory array 42 and outputs data read from the memory array 42 over input/output (I/O) data lines. Data is read from the cells of the memory array 42 by activating a word line (via the row decoder 44), which couples all of the memory cells corresponding to that word line to respective bit lines, which define the columns of the array. One or more bit lines are also activated. When a particular word line is activated, the sense amplifier within circuit 46 that is connected to the proper bit lines (i.e., column) detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line by measuring the potential difference between the activated bit line and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
The sense amplifier circuit 46 used in DRAM devices is typically arranged as banks of individual sense amplifiers. Common connections are used to activate the banks of sense amplifiers. A bank of sense amplifiers has many, e.g., two hundred and fifty-six, sense amplifiers adjacent to each other. FIG. 3 illustrates a typical sense amplifier 46 found in a DRAM sense amplifier bank. The sense amplifier 46 includes four isolating transistors 80, 82, 88, 90, two input/output (I/O) transistors 84, 86, a p-sense amplifier circuit 70 and an n-sense amplifier circuit 60.
The first isolating transistor 80 is connected such that its source and drain terminals are connected between a first sense amp line SA and a first bit line DLa. The first bit line DLa is also connected to memory cells (not shown) within the memory array 42 (FIG. 2). Similarly, the third isolating transistor 88 is connected such that its source and drain terminals are connected between the first sense amp line SA and a second bit line DLb. The second bit line DLb is also connected to additional memory cells (not shown) within the memory array 42 (FIG. 2). The second isolating transistor 82 is connected such that its source and drain terminals are connected to a second sense amp line SA— and a third bit line Dla—, which during a sensing operation is typically driven to a complementary state relative to the first bit line DLa. The third bit line Dla— is also connected to memory cells (not shown) within the memory array 42 (FIG. 2). The fourth isolating transistor 90 is connected such that its source and drain terminals are connected to the second sense amp line SA— and a fourth bit line Dlb—. The fourth bit line Dlb— is also connected to memory cells (not shown) within the memory array 42 (FIG. 2).
The gate terminal of the first and second isolating transistors 80, 82 are connected to a first isolation gating line ISOa— while the gate terminal of the third and fourth isolating transistors 88, 90 are connected to a second isolation gating line ISOb—. All four of the isolating transistors 80, 82, 88, 90 are n-channel MOSFET (metal oxide semiconductor field effect transistor) transistors. The isolating transistors 80, 82, 88, 90 and the isolation gating lines ISOa—, ISOb— form isolation devices. The normal state for the isolation gating lines ISOa—, ISOb— is a high signal. For the sense amplifier 46 that is adjacent to the selected memory array 42, the isolating transistors 80, 82, 88, 90 that do not connect directly to the selected array are driven to ground (via the isolation gating lines ISOa—, ISOb—). This isolates the deselected array from the active sense amplifier.
The first I/O transistor 84 is connected between a first I/O line IO and the first sense amp line SA and has its gate terminal connected to a column select line CS. The second I/O transistor 86 is connected between a second I/O line IO— and the second sense amp line SA— and has its gate terminal connected to the column select line CS. The I/O transistors 84, 86 are also n-channel MOSPET transistors. The I/O lines IO, IO— are used by the circuit 46 as a data path for input data (i.e., data being written to a memory cell) and output data (i.e., data being read from a memory cell). The data path is controlled by the column select line CS, which is activated by column decoder circuitry 48 (FIG. 2) of the DRAM.
The p-sense amplifier circuit 70 includes two p-channel MOSFET transistors 72, 74. The n-sense amplifier circuit 60 includes two n-channel MOSFET transistors 62, 64. The first p-channel transistor 72 has its gate terminal connected to the second sense amp line SA— and the gate terminal of the first n-channel transistor 62. The first p-channel transistor 72 is connected between the second p-channel transistor 74 and the first sense amp line SA. The second p-channel transistor 74 has its gate terminal connected to the first sense amp line SA and the gate terminal of the second n-channel transistor 64. The second p-channel transistor 74 is connected between the first p-channel transistor 72 and the second sense amp line SA—. A p-sense amplifier latching/activation signal ACT is applied at the connection of the two p-channel transistors 72, 74.
The first n-channel transistor 62 has its gate terminal connected to the second sense amp line SA— and is connected between the second n-channel transistor 64 and the first sense amp line SA. The second n-channel transistor 64 has its gate terminal connected to the first sense amp line SA and is connected between the first n-channel transistor 62 and the second sense amp line SA—. An n-sense amplifier latching/activation signal RNL* is applied at the connection of the two n channel transistors 62, 64. The sensing and amplification of data from a memory cell is performed by the p-sense and n-sense amplifier circuits 70, 60, respectively controlled by the p-sense and n-sense activation signals ACT, RNL*, which work in conjunction to effectively read a data bit which was stored in a memory cell.
FIG. 4 illustrates an exemplary portion of the DRAM circuit 40 having banks of sense amplifiers 46a, 46b, 46c and gaps 50a, 50b between the sense amplifiers 46a, 46b, 46c. Although not shown, the two sense amplifier activating signals RNL* and ACT (described above with reference to FIG. 3) are typically generated by drivers located within the gaps 50a, 50b. FIG. 4 also illustrates three sub-arrays 42a, 42b, 42c of memory cells and row drivers 52a, 52b, positioned between the sub-arrays 42a, 42b, 42c.
The gaps 50a, 50b occupy a relatively small area of the DRAM 40 compared to the amount of circuitry (e.g., RNL* and ACT drivers) necessary to be designed in the gaps 50a, 50b. There are a number of design considerations that affect the gap design and the number of sense amplifiers in a bank of sense amplifiers. For example, the word line length is usually maximized to achieve the fewest number of decoders while still meeting the DRAM chip's performance requirements. If the word line is too long, then the RC delay becomes prohibitive. A second consideration is to keep the IR drop across the RNL* and ACT buses within acceptable limits. Both the RNL* and ACT signal lines are connected to buses that stretch into the gaps. The IR drop across these buses is a function of the number of sense amplifiers in the bank and the width of the RNL* and ACT buses. Because the area that a sense amplifier occupies is minimized, the width of the RNL* and ACT buses is constrained. A third consideration that will determine the number of sense amplifiers in a bank is the width of the RNL* and ACT drivers that are placed into the gaps. The greater the number of sense amplifiers, the greater the width of the drivers.
In some prior designs, one of the RNL* or ACT drivers is placed into the sense amplifier, while the other driver is placed into the gap. The area occupied by the sense amplifier increases, but this tradeoff may be made for many reasons: 1) additional driver size, i.e., a size beyond what could have fit into the gap, was needed and/or 2) busing requirements through the sense amplifier were large enough that the additional area required for the driver transistors was free. Once one of the drivers is embedded into the sense amplifier, there is exists more area in the gap for the other driver. This scheme, however, requires large sense amplifiers and circuitry in the gaps.
Placing the drivers into different gaps is another method that purportedly increases the widths of the RNL* and ACT drivers. That is, one gap would have the ACT driver and another gap would have the RNL* driver. This method reduces the amount of wasted chip area by separating the drivers. That is, because the ACT driver usually includes a p-channel transistor and the RNL* driver usually includes an n-channel transistor, there is a minimum spacing requirement between the drivers (i.e., transistors). This space requirement between the n-channel and p-channel transistors (if implemented adjacent each other) is a large wasteful area that could have been used for additional driver width. Having the drivers in different gaps reduces this problem, but it is not an optimal solution particularly in light of new DRAM architectures.
New DRAM architectures, ones employing global word lines, make it very difficult to have adequate device widths for the RNL* and ACT drivers. FIGS. 5 and 6 illustrate a typical global word line architecture/scheme 100 and a DRAM 140 implementing the scheme 100. In the global word line scheme 100, one large row decoder/driver 102 replaces the multiple repetitive decoders/drivers 52a, 52b (FIG. 4) used in other DRAM architectures. The scheme 100 uses a metal global word line GLOBAL WL 118 and a series of polysilicon sub-word lines SUB WL 118a, 118b, 118c, 118d. In the global word line scheme 100, array breaks (or gaps) exist where the polysilicon sub-word lines SUB WL 118a, 118b, 118c, 118d are strapped to the metal global word line GLOBAL WL 118.
The DRAM 140 implementing the global word line scheme 100 contains banks of sense amplifiers 46a, 46b, 46c, 46d, sub-arrays 42a, 42b, 42c, 42d of memory cells, row drivers 152a, 152b, gaps 150a, 150b, mini-gaps 154a, 154b, 154c, 154d and word line contact blocks 156a, 156b, 156c, 156d. The mini-gaps 154a, 154b, 154c, 154d are much smaller than the gaps 150a, 150b because they occur at the word line strapping areas (as a result of the global word line scheme 100). The mini-gaps 154a, 154b, 154c, 154d, unfortunately, are too small to contain adequately sized RNL* and ACT drivers. This forces the designer of the DRAM 140 to use inadequate sense amplifier drivers or to waste precious space on the chip to implement adequate ones.
Accordingly, there is a desire and need to implement adequately sized sense amplifier drivers that will improve sense amplifier operation in a DRAM memory device without wasting precious space in the device.